The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further dramatic scaling down or micro-miniaturization of the physical dimensions of circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, such as the inclusion of lightly doped drain structures, multiple implants for source/drain regions, silicidation of gates and source/drains, and multiple sidewall spacers, for example.
The drive for high performance requires high speed operation of microelectronic components requiring high drive currents in addition to low leakage, i.e., low off-state current, to reduce power consumption. Typically, the structural and doping parameters tending to provide a desired increase in drive current adversely impact leakage current.
Metal gate electrodes have evolved for improving the drive current by reducing polysilicon depletion. However, simply replacing polysilicon gate electrodes with metal gate electrodes may engender issues in forming the metal gate electrode prior to high temperature annealing to activate the source/drain implants, as at a temperature in excess of 900° C. Such fabrication techniques may degrade the metal gate electrode or cause interaction with the gate dielectric, thereby adversely impacting transistor performance.
Replacement gate techniques have been developed to address problems attendant upon substituting metal gate electrodes for polysilicon gate electrodes. For example, a polysilicon gate is used during initial processing until high temperature annealing to activate source/drain implants has been implemented. Subsequently, the polysilicon is removed and replaced with a metal gate.
Additional issues arise with lateral scaling, such as the formation of contacts. For example, once the contacted gate pitch gets to about 70 nanometers (nm) or below, there is not enough room to land a contact between the gate lines and still maintain reliable electrical isolation properties between the gate line and the contact. Various self-aligned contact (SAC) methodologies have been developed to address this problem. To realize a SAC compatible with replacement gate techniques, two nitride liners are required to be present in the gate structure for the purpose of blocking ionic diffusion from an interlayer dielectric (ILD) oxide material layer, which is typically present adjacent to the gates, during chemical mechanical planarization (CMP) steps, which are often used during the replacement gate forming process. Conformal atomic layer deposition (ALD) methods are currently used to deposit these nitride liners. However, ALD reduces the space available for SAC opening between gates. As such, these current methodologies do not provide enough space between gates to allow for SAC formation therebetween.
A need therefore exists for an improved methodology enabling the fabrication of semiconductor devices including integrating both metal replacement gates and self-aligned contacts for small-scale architectures. Further, there exists a need for an improved methodology enabling the fabrication of semiconductor devices that provide more space for contacts in devices with a small gate pitch. Still further, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings, the brief summary, and this background of the invention.